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Digital VLSI Design with Verilog && CD

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发表于 2018-8-14 11:14:34 | 显示全部楼层 |阅读模式
Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute  
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.
In a nominal schedule of 12 weeks, two days and about 10 hours perweek, the entire verilog language is presented, from the basics toeverything necessary for synthesis of an entire 70,000 transistor,full-duplex serializer - deserializer, including synthesizable PLLs.
DigitalVLSI Design With Verilog is all an engineer needs for in-depthunderstanding of the verilog language: Syntax, synthesis semantics,simulation, and test. Complete solutions for the 27 labs are providedon the accompanying CD-ROM. For a reader with access to appropriateelectronic design tools, all solutions can be developed, simulated, andsynthesized as described in the book.
A partial list of designtopics includes design partitioning, hierarchy decomposition, safecoding styles, back-annotation, wrapper modules, concurrency, raceconditions, assertion-based verification, clock synchronization, anddesign for test.

Digital VLSI Design with Verilog_1.rar

3.99 MB, 阅读权限: 10, 下载次数: 0, 下载积分: 芯币 -6

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